The present invention relates, generally, to the field of semiconductor manufacturing, and more particularly to fabricating field effect transistors.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for field effect transistors (hereinafter “FET”) as part of advanced integrated circuits (hereinafter “IC”), such as central processing units (hereinafter “CPUs”), memory, storage devices, and the like. A vertical transport FET or vertical FET is a structure in which current flow is in the vertical direction flowing between a source/drain at a top of a fin and a second source/drain adjacent to a bottom of the fin, and a wrap-around gate surrounding a middle portion of the fin.
As demands to reduce the dimensions of transistor devices continue, vertical-type transistors such as vertical field effect transistors (vertical FETs or VFETs) help achieve a reduced FET device footprint while maintaining FET device performance. A vertical FET may use less surface area of a die than conventional FETs, which is needed with shrinking design rules.
In VFETs, the gate may be formed by a blanket metal stack deposition. To isolate and form individual devices and provide landing pads or connection pads for contacts, the gate metal of a fin may be patterned to electrically isolate from the gate metal of an adjacent fin. One technique to do this is direct gate patterning. Direct gate patterning consists of a lithography, dry etch and wet etch steps. It is important to avoiding damaging the gate metal during patterning to avoid device degradation. It may be challenging to strip lithography layers to perform the gate cut without simultaneously damaging the gate metal.